In the semiconductor industry, there has been an increasing interest in enhancing performance of complementary metal oxide semiconductor (CMOS) devices by replacing conventional silicon-on-insulator (SOI) substrates with strained semiconductor-on-insulator (SSOI) substrates. The reason behind this interest is that SSOI substrates provide higher carrier (electrons/holes) mobility than a conventional SOI substrate. The strain in the SSOI substrates can either be compressive or tensile.
Conventional methods to fabricate SSOI substrates typically require a layer transfer process wherein a strained Si-containing layer located on a relaxed SiGe layer is transferred onto a handle wafer. In particular, the conventional process includes first creating a relaxed SiGe layer of a few microns in thickness on a surface of a Si-containing substrate. The relaxed SiGe layer typically has an in-plane lattice parameter that is larger than that of Si. Next, a Si-containing layer is grown on the relaxed SiGe layer. Because the SiGe layer has a larger in-plane lattice parameter as compared to Si, the Si-containing layer is under strain.
The structure, including the strained Si-containing layer located on a relaxed SiGe layer, is then bonded to a handle wafer, which includes an insulating layer, such as an oxide layer. The bonding occurs between the strained Si-containing layer and the insulator layer. The Si-containing substrate and the relaxed SiGe layer are then typically removed from the bonded structure to provide a strained Si-on-insulator substrate.
The conventional SSOI substrate preparation method described above is quite expensive and low-yielding because it combines two rather advanced substrate technologies, i.e., high-quality, thick SiGe/strain Si growth, and wafer bonding. Moreover, the conventional preparation method is unattractive for manufacturing a large volume of substrates.
In view of the above, a cost effective and manufacturable solution to fabricate SSOI substrates is required for future high-performance Si-containing CMOS products.
Co-assigned U.S. Pat. No. 7,172,930 to Adams et al. provides one example of an alternative method that can be used in fabricating an SSOI substrate. The method disclosed in the '930 patent includes first providing a structure that contains a substrate, a relaxed semiconductor layer on the substrate, a doped and relaxed semiconductor layer on the relaxed semiconductor layer, and a strained semiconductor layer on the doped and relaxed semiconductor layer. Next, the doped and relaxed semiconductor layer beneath the strained semiconductor layer is converted into a buried porous layer and thereafter the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. An electrolytic anodization process is disclosed in the '920 patent for forming the buried porous layer.
Despite the cost efficient and manufacturable solution provided for by the '920 patent there is still a need to provide other methods of forming SSOI substrates that are cost efficient, manufacturable, and avoid utilizing a wafer bonding processing step.